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High-speed,
high-performance, and high-code-efficiency built-in RX CPU
High speed: 100MHz; high performance: 165DMIPS@100MHz (1.65MIPS/MHz) Built-in
multiply-divide unit, multiply-and-accumulate unit, and single-precision
floating point unit (FPU)
The RX CPU has achieved a maximum operating frequency up to 200MHz. It is the
next-generation CPU core that adopted high-speed features such as 5-stage
pipeline, Harvard architecture, out-of-order execution, as well as multiply and
accumulate unit, and FPU. With the RX610 Group, high processing performance of
1.65MIPS at 1MHz (165DMIPS at 100MHz) has been achieved.
Low power consumption
Output current is about 50mA, even at the fastest-speed operation at 100MHz.
This translates to 0.5mA per 1MHz, about half that of Renesas’ existing
products.
Equipped with large-volume high-speed
memory
The maximum memory capacity is 2MB with a 128KB RAM. The 2MB flash memory is of
high-speed MONOS (Metal Oxide Nitride Oxide Silicon) structure, without wait
states at speeds up to 100MHz. Combined with more than 30% improvement in code
efficiency compared to Renesas’ existing products, it is highly useful for
large-scale applications that require high-speed processing. In addition, a
128KB SRAM and a data flash with 30,000 erase/write cycles are mounted to
eliminate the need for external SRAM or EEPROM.
Enhanced built-in
functions
In addition to enhanced standard functions such as serial communications and
timer, the new products incorporate a variety of popular functions used in
existing Renesas products, including DMAC (Direct Memory Access Controller) to
perform high-speed data transfer in place of the CPU, DTC (Data Transfer
Controller) to make data transfer efficient, and CMT (Compare Match Timer)
useful for interrupt and polling. Moreover, a multi-layer structure was adopted
for the internal bus of the RX600 series to separate the data transfer path,
enabling a high-speed external transfer using DMAC and DTC.
High-speed and
multi-channel A/D
The products are equipped with four units of 10-bit 4-ch high-speed A/D
convertors, the minimal conversion time of which is 1μs (offering a total of 16
ch.). Simultaneous sampling between units and independent operation can be
set.
Thoughtful pin
assignment to support multi-pin designs
There are 144-pin LQFP and 176-pin BGA packages available. They feature a large
number of active pins. The pin assignment is pursuant to the concept of
in-family upward compatibility that has been popular with M16C to facilitate
board layout at the time of replacement. The pin assignment is also excellent
in terms of EMC performance.
Integrated
development environment and excellent migration support
Software development is supported by Renesas’ integrated development
environment called High-performance Embedded Workshop, together with the C
compiler, RTOS, three emulators and other development tools. The compiler
facilitates program migration from existing C programs for the CPU to
effectively protect customers’ development assets and their utilization into
the future.
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